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Advanced Cadence Software Tutorial
Outline of the Tutorial
Layout of an Inverter in Virtuoso
To begin this tutorial, we need to start the Cadence software packages with the icfb& command. We will also need to create a new library and a new cell view within this library. Attach this library to the NCSU TSMC3 technology library (.25um process). We need to set the View Name to layout and the tool to Virtuoso. Once the new library and cell view are created, we will be ready to begin. This library and cell view will be used for parts 1 and 2 of this Advanced Tutorial.Once the Cell View has been created, the Virtuoso editor window will be opened. Along with the editor window, a layer selection window LSW will be opened. This window can be seen in figure 1.
Figure 1. Layout and Layer Selection Windows
There are specific layers that we will use for this tutorial. If the following layers are not present in the list of layers in the LSW you will need to add them to the list.
To add layers to the list, click on LSW->Edit->Set Valid Layers and check the boxes next to the desired layers. When finished click OK.We will now begin to create our inverter layout. The first step that must be taken (Every time you start Virtuoso!) is to change the snap, or lambda to 0.15. To do this, click on Options->Displayand change the X snap spacing and Y snap spacing from 0.075 to 0.15 (NOTE: In the NCSU Libraries, lambda is 1/2 the NCSU size, i.e. NCSU TSMC4 has a lambda of .2).
We will create this inverter be drawing rectangles, click Create->Rectangle. To stop drawing rectangles, press <ESC> to exit from the Create Rectangle command. Rectangles are drawn by clicking on the selected layer and then in the editor window, click where you want the first corner and drag to the desired location of the opposite corner. There are X and Y coordinates at the top left of the editor window. We will now begin to draw the inverter.
We will build a PMOS transistor and a NMOS transistor by drawing rectangles in various layers. We will use scalable Nwell submicron technology and the layers below are layers with drawing purpose. Please draw each of them carefully and frequently save your work.
Layer First Corner Second Corner pselect dg (-0.30, -0.30) (2.10, 2.55) nselect dg (-0.30, -3.15) (2.10, -0.30) pactive dg (0.00, 0.00) (1.80, 2.10) nactive dg (0.00, -2.70) (1.80, -2.10) poly dg (0.75, -3.00) (1.05, 2.40) nwell dg (-0.90, -0.90) (2.70, 3.75)
Your progress so far should look similar to the image in figure 2.
Figure 2. Inverter Layout
Next we will lay down the metal and contacts for the sources and drains.
Layer First Rectangle Second Rectangle Third Rectangle metal1 dg (0.00, 0.00), (0.60, 2.70) (1.20, -2.70), (1.80, 2.10) (0.00, -3.30), (0.60, -2.10) ca dg (0.15, 0.15), (0.45, 0.45) (0.15, 0.90), (0.45, 1.20) (0.15, 1.65), (0.45, 1.95) ca dg (1.35, 0.15), (1.65, 0.45) (1.35, 0.90), (1.65, 1.20) (1.35, 1.65), (1.65, 1.95) ca dg (0.15, -2.55), (0.45, -2.25) (1.35, -2.55), (1.65, -2.25) None
Your layout should now look similar to that of figure 3.
Figure 3. Inverter Layout
We will now add the contacts for connections to the power supplies.
Layer First Rectangle Second Rectangle metal1 dg (-0.30, 2.70), (2.10, 3.30) (-0.30, -3.90), (2.10, -3.30) ca dg (0.15, 2.85), (0.45, 3.15) (0.15, -3.75), (0.45, -3.45) nselect dg (-0.30, 2.40), (0.90, 3.60) None nactive dg (0.00, 2.70), (0.60, 3.30) None pselect dg (-0.30, -4.20), (0.90, -3.00) None pactive dg (0.00, -3.90), (0.60, -3.30) None
Your layout should now look similar to the one in figure 4.
Figure 4. Inverter Layout
We will now add the locations for the input and output pins.
Layer First Rectangle Second Rectangle metal1 dg (0.00, -1.05), (0.60, -0.45) (0.15, -1.65), (0.75, -1.05) metal2 dg (0.00, -1.05), (0.60, -0.45) (1.20, -1.05), (1.80, -0.45) via dg (0.15, -0.90), (0.45, -0.60) (1.35, -0.90), (1.65, -0.60) poly dg (0.15, -1.65), (0.75, -1.05) None cp dg (0.30, -1.50), (0.60, -1.20) None
The layout should now look finished, but it is not. We need to let the router know how to connect the cell to others. We need to create locations for the pins in, out, vdd!, and gnd!
Click Create->Pin. This will open a form for creating pins. We would like to make shape pins, so we need to select the shape pin on this form. We would also like to add the pin label to the schematic, so we need to select Create Label on the form. The form can be seen in figure 5.
Figure 5. Shape Pin Window
NOTE! If you add a pin and it does not look (color, pattern) like the desired layer type (metal1, metal2, etc.) it is not the desired layer type. Undo the addition of the pin and check all of your settings. At times, I have had to close the Create Pin window and re-open it.
We will start with the in and out pins. These pins should be metal2 pins. To select metal2 from the sym pin form. You can alternate between the sym pin form and shape pin form by selecting the appropriate button. Make sure that you are in the shape pin form when placing the pins on the layout. Once metal2 has been selected, specify the name of the pin as in, select input as the I/O type, andTop and Bottom only as the access direction. Click at (0.00, -1.05) and drag to (0.60, -0.45) to place the pin and click at (0.30, -0.75) to place the label. For the out pin, we will need to do a similar process, but the I/O direction needs to be output. Place the pin at (1.20, -1.05) to (1.80, -0.45) and place the label at (1.50, -0.75).
We now need to add the vdd! and gnd! pins. These pins should be metal1 with access directions of left and right, and inputOutput as the I/O type. Make sure the names are vdd! and gnd! because these are reserved for power pins. Vdd should be placed at (-0.30, 2.70) to (2.10, 3.30) and the label at (0.90, 3.00). The gnd pin should be placed at (-0.30, -3.90) to (2.10, -3.30) and the label at (0.90, -3.60). Click Hide to finish creating the pins. Your inverter should now look like the one in figure 6.
Figure 6. Finished Inverter Layout
This design does have some errors, but we will take care of them in the next section. We will use these errors to familiarize ourselves with Design Verification tools that are part of the Cadence packages.
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