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Advanced Cadence Software Tutorial Part 3
Layout Generation from a Schematic
In this section, we will look at how to create a layout from a previously created schematic circuit design. In the following session Layout vs. Schematic, we will use a powerful tool in the Cadence package to compare our layout to our schematic. This will allow us to be more confident that our layout will function similarly to the simulated schematic.First, begin by opening the schematic of the inverter that we used during the Basic Tutorial. We also need to note the technology that the inverter was designed in. There are a few ways this can be done, we can view the properties of the library or we can look at the text around the transistor. In this case, we will look at the text around the transistor. The PMOS transistor can be seen in figure 12.
Figure 12. Technology details around PMOS transistor
In this example we are using the tsmc 25um technology. In the NCSU libraries, this is NCSU TSMC3, therefore, lambda will be .15. This lambda value will need to be remembered for later use in this tutorial.
Now that we have opened the inverter and we know the technology, we are ready to generate the layout. Click Tools->Design Synthesis->Layout XL and a window will pop-up asking if you wish to open an existing layout, or create a new layout. In this case, we will want to create a new layout. This will bring up another window asking for the Cell name (the same name as your inverter) and the View Name: Layout. Click Ok and this will start Virtuoso under a special mode for generating Layouts from schematics.
Once all windows are open, and you have arranged them as desired, we are ready to begin. First, change the X and Y snap to .15 (or what ever value of lambda you need). After you have set the value for lambda, click Design->Gen From Src… to open a window that will allow you to set the parameters for your layout. The window should look like the window in figure 13.
Figure 13. Layout generation from source form
We are able to set many things in this window, we will go through them step by step.
- Change the in Pin Type to Geometric, the Layer Master to Metal2, and the Width and Height to 4 x lambda.
- Change the out Pin Type to Geometric, the Layer Master to Metal2, and the Width and Height to 4 x lambda.
- Change vdd and vss to Pin Type Geometric, the Layer Master to Metal1, and the Width and Height to 4 x lambda.
- Set Pin Label Shape to Text Display.
- Click OK
This should place some boxes in the layout window. One box for PMOS, NMOS, in, out, vdd, and vss. There should also be a large purple box in the upper right quadrant of the layout window. This is the boundary line, and the layout needs to fit within this line. The layout window should look similar to figure 14.
Figure 14. Generated layout window
You can change the display levels to From 0 To 20 to see the internal parts of the blocks, but you will not be able to edit them. Move these blocks to their proper location within the purple boundary. Note the lines that indicate where connections will need to be made. Place the PMOS about 3/4 of the way up from the bottom of the boundary, place the NMOS 6 x lambda below it. Place the outpin contact between the PMOS and NMOS so that it is in line with the drains of the two MOSFETS. Place the in pin at the same level vertically as the out pin, but position is so that its right edge is 4 x lambda from the left edge of the line that would connect the two poly gates. Position vdd and vss in their correct locations above PMOS or below NMOS respectively. Make sure there is 2 x lambda between the edge of the pin and the nselect or pselect region. Your design should now look similar to figure 15.
Figure 15. All components moved to correct locations
We now need to make some modifications so that our design will pass the DRC. First, we will make the well contact for the PMOS. This contact will be made to the vdd pin. We first need to add a region of nwell, around the vdd contact. This region should be as long as the existing region, it should touch or overlap the existing region, and it should extend 3 x lambda above the vdd pin. We next need to add a region of nselect around the vdd pin with a spacing of 2 x lambda all the way around. This should leave a space of lambda between the top of the nselect and the nwell. We next need to add a region of nactive, this should be placed in the same place as the vdd pin and it should be the same size. We also need to add a contact that is 2 x lambda by 2 x lambda in the center of the vdd, nactive box. Your design should look similar to figure 16.
Figure 16. Addition of nwell, nselect, and nactive for nwell contact
We also need to place a pactive region similar to the nactive region at the location of the vss pin. We will need to surround it with a pselect region following the same rules as above. The only difference with adding the region around vss compared to vdd is the existence of the well around vdd. We also need to add a contact with the same dimensions as before.
Next, we need to connect the devices. Begin by adding a rectangle of metal1 that connects the drains of the transistors. This should go right over the out pin. We will now add a via in the middle of the out pin region with the same dimensions as the contacts above. Next, draw a rectangle of poly connecting the gates of the transistors. We will return to the gates later to make the connection with the in pin. Next, make metal1 rectangles connecting the sources of the transistors, to their respective power pins, vdd or vss. The layout should now look similar to figure 17.
Figure 17. Metal1 connections made to connect transistors and pins
Our next step is to connect the in pin to the poly gates. Make a metal1 rectangle that is the same height as the in pin and that covers the in pin and comes to the edge of the poly. This would be a 8 x lambda by 4 x lambda rectangle. Next, create a via of the same dimensions as before that connects the metal1 with the metal2 of the in pin. Next, create a poly rectangle that is 6 x lambda by 4 x lambda that covers the metal1 and the poly. Then create a contact with the same dimensions as before from the metal1 to the poly. The layout should now look like figure 18.
Figure 18. Connection made to IN pin
Finally, save the layout and run DRC. There should be no errors. If there are errors, find them and fix them. You are now ready to extract the layout and run LVS.
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