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Advanced Cadence Software Tutorial Part 2
DRC Verification and Generation of Netlist
In this tutorial, we will verify our inverter layout by Design Rule Checking (DRC) and Spectre netlist extraction. You can learn about the layout rules here.Checking the rules is a relatively simple process, but it can take some time. First, make sure that your layout is open in Virtuoso. Click on Verify->DRC. This will bring up a DRC form. Make sure that the rules library is the same as the technology library. If it is correct press OK, in most cases this will be correct and you can just press OK. This checking process can take a while. All of the rules and errors will be displayed in the CIW. Upon completion, the DRC errors will flash on the Virtuoso window.
To see what the errors are, click Verify->Marker>Explain, and then click a flashing error on the design. This will bring up a window with an explanation of the rule violation. The design and the rule explanation window can be seen in figure 7.
Figure 7. DRC Markers Explanation Window with Layout in Background
We now need to fix these errors before we can go any further.
1. Select Edit->Other->Chop
2. Select the nselect for the NMOS by clicking the left button. You can see that the nselect rectangle is highlighted.
3. Click on (-0.30, -3.15) and (0.90, -3.00) to chop the overlap away. Do the same for the excess pselect region for the PMOS.
Once the Chop has been made, you will need to run DRC to make sure everything in correct. You should get no errors this time. Save your design before you go any further. Your layout should look like the one in figure 8.
Figure 8. Final Layout after all DRC errors are corrected
Generate an Extracted View
We need to generate an extracted view so that we can later create the netlist. To generate the extracted view,
1. If the layout is not open, open it now.
2. Select Verify->Extract and an extractor form will appear.
3. Make sure that the extraction method is flat, the rule file is divaEXT.rul, and the rule library is correct for your attached technology file.
4. Click Set Switches and select Extract_parasitic_caps then click OK on the Set Switches window.
5. Click OK on the Extractor Window.
The Cadence Extractor will extract the layout and save it as the extracted view. You will see the extracted view appears in the Library Manager. You can now close the layout and open the extracted view. If the layout is changed in the future, you must extract the layout again. Change the snap of the extracted view from 0.075 to 0.15 as we did before.
The extracted view should look like the one in figure 9.
Figure 9. Extracted View of the Layout
To see the details of the extracted view, you can change the display level. To do this click Option->Display. This will bring up the display options window. Change the Display Level from 0 to 20 and click OK. The result of this display level change should look like the image in figure 10.
Figure 10. Extracted View with Display Levels from 0 to 20
Generate a Spectre Netlist
The creation of a Spectre netlist will allow us to simulate our inverter design. With the Extracted view open, we first need to start the Analog Artist environment. This is done by clicking Tools->Analog Environment, which will open the Analog Artist window.
The first step is to setup the Analog Artist environment. First click Setup->Simulator/Directory/Host. Set the simulator to Spectre. Setup the project directory to a directory where you would like the result files to be saved. Next we need to setup the model path. Click Setup->Model Path to set the path of the files to be included. For this example (.25um process) the models are tsmc25P.m andtsmc25N.m in the directory /opt/cadence/NCSU_1.2/local/models/spectre/standalone/. Once this is all done, click the Green Traffic Light to start the process of generating a Spectre Netlist. If no warnings or errors occur, the netlist will be saved in the previously setup directory/inv/spectre/extracted/netlist/input.scs.
To simulate the file type spectre input.scs at the command line. (input.scs is assumed to be the name of the edited file for simulation)
To plot the data, type awd -dataDir input.raw/ at the command line. (again “input” is assumed to be the name of the edited file.
This will bring up some windows that will allow you to plot the data. The “Result Browser” contains the data that can be plotted in the “tree”. Yellow nodes can be plotted by right clicking on the node. These are plotted in the “Waveform Window”. An example of the Waveform Window and the Result Browser are in figure 11.
Figure 11. Two examples of Waveform and Results Browser windows. The top is DC analysis, and the bottom is Transient analysis
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