Often, it is difficult for a new user to understand the relationship between all of the different tools provided by Cadence. Here we will try to describe and document the different tools we use. We will update this as we learn more about the different tools. Send a message to one of the technical contacts if you see something incorrect, or would like to update or add material.
Cadence tools are used for the design of integrated circuits. Cadence has products for designing circuits at an analog level using Spectre. Digital circuits can be designed using Hardware Definition Languages (HDL). These include VHDL and Verilog. They provide high-level descriptions of circuit operation. They can be used to simulate large, complex, digital circuits at the logic level.
The next step is to generate a layout from the HDL or schematic. This can be done automatically with standard cells or by hand. Often, analog circuits are done by hand. Digital circuits are typically done automatically due to the large number of gates. Tools are available to automatically place cells and connect them together.
Next, the design must be verified. This includes checking the design for layout rule violations and making sure the layout matches the schematic. These are known as DRC and LVS, respectively.
If the design matches, it is often useful to extract parasitic elements such as resistors and capacitors that result from the layout. The circuit can be re-simulated including the parasitic components. If the results are not within specifications, the layout may need to be reconsidered, or design changes to the circuit may need to be made.
In some cases, especially with mixed-signal circuits, it may be necessary to perform a substrate noise analysis.
Finally, once the design has been tested and verified, it is ready to send to fab. A GDSII file can be exported and sent out.
Spectre is an analog and mixed-signal simulator. It is performs similar functions as SPICE. Spectre can read in SPICE netlists, but it has its own, more powerful language. Spectre is part of the IC 5.0.33 package. Use the command spectre from the command line to invoke the simulator. A GUI is also available through Virtuoso.
Use Wavescan to view the output of Spectre simulations.
Virtuoso is a graphical interface for designing circuits through a schematic interface. It also is used for designing cells and circuits at the layout level.
ICFB (IC front-to-back) is a high-level menu-driven “shell” for many of the tools in the IC package. From the Tools menu, you can select many tools. One of the more useful is Library Manager.
Library manager gives the user access to the different design libraries. A library contains different cells. Each cell has different views. For instance, the library may be an 8-bit counter. The different cells may be d-flip-flops, nand gates, and inverters. Each cell may have a schematic view, symbol view, and a layout view.
Silicon Ensemble is a tool for automatic layout generation of complex digital circuits. It takes an LEF file and a Verilog structural description of a circuit and can perform cell placement and wire routing.