Silicon Ensemble Tutorial – written by Philippe Adell
Silicon Ensemble Tutorial – written by Philippe Adell
The objective of this tutorial is to provide insight on how to use Cadence tools to design an application specific digital integrated circuit. This tutorial details the steps that have been followed to obtain the layout and schematic of a digital circuit (~2500 gates) from a VHDL behavioral description.
The project illustrated in this work is part of the DC/DC switching power converter project that is developed at Vanderbilt University in collaboration with the Polarfab foundry (www.polarfab.com). The goal of this project is to develop a radiation-tolerant integrated switching DC/DC power converter.
SEMI-CUSTOM APPROACH DESIGN FLOW
The final design will contain several thousand logic gates which translates to several tens of thousands of transistors. It is extremely error prone (and impossible!) to do this magnitude of design and layout by hand. For this design approach, we will first write a description of how the circuit behaves. In the most simple case, such as a state machine, for a given set of inputs we will specify what the outputs will be. A compiler tool will translate the behavioral description into a gate-level description of the circuit, or netlist. That is, it synthesizes the behavioral description. The circuit will be compiled with pre-defined cells from a standard cell library. The standard cell library will contain the electrical characteristics of the circuit, timing information, and layout information for each gate. Next, the synthesized netlist of the circuit is read into Virtuoso, where it will be represented as a schematic. At this point, the circuit may be simulated with an analog simulator to verify correct operation. Next, a layout is generated from the schematic. The first step of this is to generate and place the cells. The next step is to connect them together. This can be done with an automated tool with the options to minimize certain characteristics such as area, power, or delay. From the layout, parasitic components may be extracted, and the circuit re-simulated. If specifications are not met, changes to the layout may need to be made in order to correct the problem. Finally, the layout can be converted into a GDSII or CIF file for fabrication.
- Step 1 => from VHDL to schematic and simulation: FRONT END
Figure 1. Front End Design flow from VHDL behavioral to Virtuoso schematic
A) VHDL behavioral description (need a text editor)
Figure 2. Example of VHDL behavioral description
The first step is to use a VHDL description of the design: files: dig_contr.vh”. A separate tutorial is being written to describe the simulation of HDL designs.
We are assuming that the functionality of the VHDL design has been checked using appropriate tools. The design can then be synthesized.
B) Synthesis: Design Compiler: Buildgates (Cadence) or Design_vision (SYNOPSYS)
Two tools can be used to synthesize the design: 1) Buildgates (Cadence) or 2) Design Vision (Synopsys). These two tools interact with the PDK technology libraries. Every PDK has its own set of libraries including all the necessary information about the cells (process information, power, capacitance, functionality, timing information…). Before using the Design Compiler tools these libraries need to be compiled.
- Buildgates needs .alf file from a .lib file (compilation tool: libcompile)
- Design_Vision needs: .db file from a .lib file (compilation tool library compiler)
When having these two compiled technology libraries, the design can be synthesized. As an example, let’s use Design_Vision.
The steps are: READ – SETUP LIBRARIES – ANALYZE – ELABORATE – COMPILE – VIEW SCHEMATIC
READ: File => read => read the file dig_contr.vhd
SETUP LIBRARIES: File => setup => setup the .db files into the target library and target physical library
ANALYZE: File => Analyze => add dig_contr.vhd
ELABORATE: File => Elaborate => elaborate the design
COMPILE: Design => compile => select ungroup all
VIEW SCHEMATIC: Schematic => New Design Schematic view
Figure 3.Structural view of the design after compilation
The schematic obtained is a display of all the gates and cannot be used in the Cadence tools directly. The synthesized design has to be saved as in a different structural format (verilog or vhdl). To import the design we use verilog_in.
Example of a structural verilog format: dig_contr.v
C) Import into Cadence schematic
We use verilog-in to import the structural verilog file obtained from the synthesis. As shown on the figure, the verilog window allows to import the dig_contr.v file. To get this window go to the icfb window => tool => import => verilog.
Figure 5. Verilog_in import window
You need to create a target library (don’t forget to attach the technology library that goes with it). In the verilog files to import, add your files. Include the digital cell libraries (PDK dependent) in the reference libraries box.
You can import it as a functional description, schematic or netlist.
Then you can then visualize your design and go down in hierarchy in each digital cell (the option (layout, veriloga description, schematic…) of the cells depend on your PDK ressources).
Figure 6. Schematic view of the design after importing the structural verilog files
D) Simulation of the design
Figure 7. Top hierarchy of the DC/DC converter circuit
The figure 8 shows variation of the transfer function versus the duty cycle for the same value of output voltage. These simulation were performed with a mixed signal approach using a combination of veriloga and analog description.
Figure 8. Simulation results
- Design Flow: step 2 => from VHDL/Verilog structural to Automatic Layout: BACK END
The back end design flow is the part of the design flow that goes from VHDL/VERILOG structural to Layout using an automatic place and route tool. The Cadence tool that we use is Silicon Ensemble. We show below a detailed tutorial on how to use Silicon Ensemble to generate the layout of the digital control automatically.
Figure 9. BACK END design flow
Figure 10. Main operating window
A) PDK files
Each PDK has its own set of files. To use Silicon Ensemble, a .lef file and a layer .map is needed. The .lef files tell where all the pins of each cell are placed and give the layout design rules. The .map file describe the .map layers. The .lef file has to be imported first.
Then, the verilog structural file, in our case dig_contr.v was imported into Silicon Ensemble. Associated with this, it is important to specify the name of the top module in the verilog top module box.
Go to Floorplan => Initialize Floorplan menu. Select Flip Every Other Row. The IO to Core Distance defines the Region for Vdd and Gnd rings. Row utilization represents the density of cells on every rows. The area of the layout can also be calculated by using the calculation button.
Figure 11. Floorplan main window
Figure 12. Floorplan window
C) Place => Place I/O
Go to place => place I/Os, place => Place Cells.
Figure 13. Place IO window
Figure 14. Place cells window
D) Add power and ground rings
Go to add power and ground rings. You can select the width of your ring and position. After go to Route => connect rings.
Figure 14. Power add rings window
Figure 15. Cell plus power rings representation
Figure 16. Connect Ring window
Figure 17. Cells + Power Rings + connectivity between the rings
Go to Route => WRoute. Select Global and Final Route and select Auto Search and Repair. (it can take sometimes: a certain number of repairs are necessary for this)
Figure 18. Route window
Figure 19. Cells + Power Rings + connection between Rings + cells routing
D) Export to GDSII
After completing the routing and make the necessary verifications, the layout can be exported using a .DEF format or a GDSII (stream format). A map file containing the layer numbers is necessary. Here is an example of a layer map file that we use for our digital block.
# Layer Map Example
# DFII DFII GDS Stream
# Layer Layer Layer Data
# Name Purpose Number Type
n_sea drawing 23 0
nburied drawing 2 0
isolation drawing 3 0
nfield drawing 5 0
chan_stop drawing 26 0
punch_stop drawing 63 0
lv_gate drawing 4 0
cap_poly drawing 8 0
gate_poly drawing 52 0
gate_poly net 52 0
gate_poly resistor 52 0
pldd drawing 57 0
nplus drawing 42 0
pplus drawing 53 0
contact drawing 6 0
met1 drawing 9 0
met1 net 9 0
via drawing 10 0
met2 drawing 11 0
met2 net 11 0
via2 drawing 20 0
met3 drawing 21 0
met3 net 21 0
Figure 20 . Layer map example
Figure 21. GDSII window
Figure 22. DEF window
E) Import into Cadence
Figure 23. Layout of the digital block
We demonstrate the use of a design flow to layout digital integrated circuit from a VHDL behavioral description to a Cadence schematic and layout. This work presents a lot of interest since it can be applied to other design.
As far as radiation effects are concerned, this type of design flow is very valuable to the radiation effects and reliability group. Radiation Hardening by Design solution can be applied1) At the cells level, mean of modifying cell libraries, 2) At the structural or behavioral synthesis code level (VHDL or verilog) 3) At the gate circuit level.
The development of this tutorial is still in progress and the development of new strategy for radiation effects using the Cadence tools is our main goal when it comes to designing complicated integrated circuits.