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2018-2019 Research Projects Using Cadence Tools

Cadence Use in the Classroom:

  • The Cadence Custom IC Design Suite of tools is extensively used in the EECE 4385 VLSI Design class (Formerly EECE 285).  The class focuses on integrated circuit design, layout, and verification as well as parasitic elements and their impact on circuit performance.  System-level design experience is gained by completing all design, layout, and functional circuit testing phases of a project.
  • The Virtuoso Schematic Editor, Analog Design Environment, and Layout Suite are used with the NCSU FreePDK at 45nm (FreePDK45).

Examples of Cadence Tool Use in Research – Team Based Design Effort with Graduate Students and Research Faculty

  • The Vanderbilt Radiation Effects Research Group and the Institute for Space and Defense Electronics setup multiple workstations dedicated to graduate student design of integrated circuits and printed circuit boards.  The area facilitates a team based approach to the design of ICs and the PCBs utilized in testing, where graduate student researchers can work collaboratively with research faculty and and experienced IC design researchers.
  • The Vanderbilt team has designed, fabricated, and tested a technology characterization vehicle in a bulk FinFET technology node, which includes operational capability at near threshold voltage, a new on-chip transient pulse measurement capability, multiple flip-flop designs for characterization in harsh environment operation, and a novel combinational logic family design that is immune to radiation-induced transient pulses.  The integrated circuit was designed with a mix of standard and custom cells with hand placement and routing using the Virtuoso Advanced Node (ICADV) suite of tools, including schematic capture and layout editor.  The Spectre Circuit simulator was extensively used for test circuit operation verification, with an without parasitic extracted elements.
  • The Vanderbilt Team designed chips had 100% yield when received back from fabrication.  The IC’s were packaged at Vanderbilt and tested with a heavy-ion accelerator at Lawrence Berkeley National Laboratory, to characterize the single-event effects response of the technology and test circuits.  This design and test effort has resulted in one of the largest single-event response databases for this technology in the world, as well as many peer-reviewed journal publications that detail the test chip design and innovation, elucidated mechanisms, and novel mitigation design techniques.
  • This effort also produced validation data sets for a new compact model to simulate single-event effects in bulk FinFET technologies.  The model is written in Verilog-AMS and integrated with PDK compact models targeted to the Spectre Circuit simulator.

Sample of 2018 – 2019 Publications that Utilized Cadence Tools in Research:

Sample of 2018-2019 Conferences Attended and Presenting Research Utilizing Cadence Tools:

  • IEEE International Reliability Physics Symposium
  • IEEE Nuclear and Space Radiation Effects Conference
  • Government Microcircuit Applications and Critical Technology Conference