SEU and Soft Error in sub-40nm bulk CMOS
Edge triggered flip-flops were designed for inclusion on test chips in 28nm and 20nm bulk CMOS technology test chips. Flip-flop designs included standard D-Flip-Flops and multi-node redundant flip-flop designs, for example DICE. Additionally combinational logic test structures were developed to feed the Flip-Flop inputs as a means of determining the significance of the propagation of single-event transients (SET) to the over all single-event upset (SEU) and soft error rates.
Circuit layouts were performed with Cadence Virtuoso Layout, with schematics in Virtuoso Schematic Composer. Analog Design Environment was utilized in performing circuit simulations with both Spectre and UltraSim to analyze functionality, speed, power, and soft error susceptibility trade-offs on the flip-flop and combinational logic designs.
Multiple publications and presentations came from this research work, included on the main 2014 activities page. The primary student working on this research will be receiving his PhD and has taken a job in the integrated circuit / FPGA industry with a large commercial company.