The goal of this project is to characterize single-event effects (SEEs) in All-Digital Phase-Locked Loops (ADPLLs) and develop radiation-hardening-by-design (RHBD) techniques against the error signatures. The Cadence EDA tool suite has been facilitating in this research in the following ways.

Circuit schematic and layout design

Cadence Virtuoso has been used for circuit schematic and layout design for two 40-nm bulk digitally-controlled ring oscillators (DCROs) and a 32-nm SOI digital finite impulse response (FIR) filter, which are essential building blocks for ADPLLs.  The 40-nm bulk DCROs have been tested using a two-photon absorption laser to simulation a high-energy heavy-ion strike to sensitive regions of the circuit, and the results and findings were presented at the 2014 IEEE NSREC and have been submitted for publication in IEEE Transactions on Nuclear Science.

Circuit electrical simulation and Single-Event Transient (SET) simulation

The Spectre simulator in the Cadence CAD tools has been used for electrical simulation of the circuit designs. Virtuoso ADE-XL  is used to facilitate running Monte Carlo simulations on the circuits under device, temperature and voltage corners. PSS simulation tool is used to simulate phase noise of the designed DCRO and ADPLL.

The ISDE bias dependent SEE current model (a derivative work of [1]) is used to inject simulated single-event currents, with simulation steps moving the source to each of the internal nodes of the circuit, to determine the single-event response of the circuit.

[1] Kauppila, J.S.; Sternberg, AL.; Alles, M.L.; Francis, AM.; Holmes, J.; Amusan, O.A; Massengill, L.W., “A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit,” Nuclear Science, IEEE Transactions on , vol.56, no.6, pp.3152,3157, Dec. 2009. doi: 10.1109/TNS.2009.2033798